1. Field of the Invention
The present invention relates to a CMOS output buffer circuit.
2. Discussion of the Related Art
As known to anyone skilled in the art, conventional CMOS output buffer circuits include a CMOS final driving stage, which in turn includes a P-channel MOSFET (pull-up) and an N-channel MOSFET (pull-down) connected in series between a voltage supply line (VDD) and a common ground (GND).
The circuits can further include a control circuitry for the activation of the CMOS final driving stage; such a control circuitry mixes the input data signal with an enable/disable signal for the activation of a so-called three-state (or high impedance) mode, in which both the MOSFETs of the final stage are off. In its most simple form, the control circuitry includes a NAND gate, at whose inputs the input data signal and the enable/disable signal are applied and whose output drives the gate of the P-channel pull-up, and a NOR gate, at whose inputs the input data signal and the enable/disable signal (complemented) are applied and whose output drives the gate of the N-channel pull-down.
An important requirement which integrated circuits need to satisfy is power-down compatibility. This means that when the power supply of the printed circuit board whereon the integrated circuits are mounted is turned off, the integrated circuits are not to be damaged and must not give rise to significant leakage currents. These characteristics are extremely important in portable electronic systems (computer, mobile phones etc.) Wherein reduced power consumption is a key feature.
An integrated device with the terminal tied to the voltage supply line VDD grounded can have a non-zero voltage applied to its input and/or output terminals. In the case of a CMOS output buffer circuit, the parasitic diode associated with the pull-up MOSFET of the final driving stage could turn on, thus damaging the device.
It is also known that there is a trend towards reducing the value of the supply voltage. A few years ago the standard for CMOS was 5 V, nowadays a lot of 3 V applications are found. It is also common to have electronic systems in which 3 V-supplied boards are interfaced with 5 V-supplied boards. In the High-speed CMOS (HCMOS) logic family interface circuits are available which allow 3 V-supplied boards to be connected to a same bus as 5 V-supplied boards.
A 3 Volts integrated circuit which, in the three-state mode, is capable of sustaining a 5 Volts at its outputs, is said to be "5 Volts tolerant".
An integrated circuit with three-state output buffer circuits of the type described above and supplied at 3 V is not 5 Volts tolerant, i.e. it cannot be connected to a bus of signals driven at an higher voltage, for example 5 V, for the following reason: the P-channel pull-up is formed inside an N type well constituting the so-called "bulk". The N-type well or bulk is connected to the voltage supply VDD, to prevent, in any operating condition, the junctions between the P-type source and drain regions of the P-channel pull-up and the bulk from being forward biased. If however the voltage supply VDD is 3 V and the voltage of the output of the final stage, i.e. the drain of the P-channel pull-up, can increase to a value of 5 V, the junction between the P-type drain of the P-channel pull-up and the bulk is forward biased, which causes a high leakage current to flow; such a current, being so high, can damage the integrated circuit.
This problem has been recognized for a long time, and solutions to it have been proposed. Some of these solutions are however not suitable for logic integrated circuits, because they involve the use of components working in the linear region, thus dissipating power.
In "Tips For Straddling The 3-V To 5-V Fence", Electronic Design, Apr. 4, 1994, 5-V tolerant three-state output buffer circuits are proposed that make use of Schottky diodes to block the leakage current. In one of the proposed solutions, the bulk of the P-channel pull-up is not connected to the voltage supply VDD directly, but through a Schottky diode; the bulk is further connected, through another Schottky diode, to the output node of the final driving stage.
The drawback of the these solutions is that they involve the use of BiCMOS (Bipolar CMOS) technologies, more expensive than the known CMOS or HCMOS technologies.
In the U.S. Pat. No. 5,270,589 (Toshiba) two output buffer circuit solutions are disclosed: in the first solution, an N-channel pass transistor is connected between the output node of the final stage (the drain of the P-channel pull-up) and the output pad; the gate N-channel pass transistor is driven by a voltage VDD' higher than VDD. This requires a second, external power supply line (which is impossible for devices having fixed pin number and configuration), or an on-chip charge pump to boost VDD to VDD'. The second solution is similar to the first solution, but the pass transistor is an N-channel depletion MOSFET with gate connected to VDD. The problem is that in some technologies depletion MOSFETs are not available.
In the U.S. Pat. No. 5,151,619 (IBM) an output buffer circuit is disclosed which makes use of a transmission gate with floating bulk to decouple the final stage from the remaining of the circuit.
In view of the state of the art described, it is an object of the present invention to provide a CMOS output buffer circuit with power-down compatibility.
It is another object of the invention to provide a CMOS output buffer circuit with three-state capability, suitable for applications wherein integrated circuits with different voltage supplies must be interfaced, which is structurally different from and overcomes the drawbacks of the known circuits.